west bridge?: astoria? usb and mass storage peripheral controller preliminary confidential cywb0224abs, cywb0224abm cywb0226abs, cywb0226abm cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 features ? n-xpress? nand controller technology ? interleave up to 16 nands with 8 chip enables (ce#) for x8 or x16 slc (cywb0224abs) or mlc (cywb0224abm) nand flash devices ? 4-bit error correction coding ? bad block management ? static wear leveling ? multimedia device support ? up to 2 sd, sdio, mmc, mmc+, and ce-ata devices ? slim? architecture, allowing simultaneous and independent data paths between the processor and usb, and between the usb and mass storage ? high speed usb at 480 mbps ? usb 2.0 compliant ? integrated usb switch ? integrated usb 2.0 transceiver, smart serial interface en- gine ? 16 programmable endpoints ? flexible processor interface, which supports: ? multiplexing and nonmultiplexing address and data inter- face ? sram interface ? pseudo cram interface (antioch interface) ? pseudo nand flash interface ? spi (slave mo de) interface ? dma slave support ? ultra low power, 1.8v core operation ? low power modes ? small footprint, 6x6mm vfbga ? supports i2c boot and processor boot ? selectable clock input frequencies ? 19.2 mhz, 24 mhz, 26 mhz, and 48 mhz applications ? cellular phones ? portable media players ? personal digital assistants ? portable navigation devices ? digital cameras ? pos terminals ? portable video recorders ? data cards and wireless dongles west bridge tm astoria tm flexible processor interface control registers uc high-speed usb 2.0 xcvr u p s slim tm access control cypress n-xpress tm engine configurable storage interface sd/sdio/ mmc+/ ce- ata block block diagram [+] feedback
cywb0224abs, cywb0224abm cywb0226abs, cywb0226abm preliminary confidential page 2 of 7 functional overview the slim? architecture the simultaneous link to independent multimedia (slim) archi- tecture allows three different interfaces (p-port, s-port and u-port) to connect to one another independently. with this architecture, connecting a device using astoria to a pc through usb does not disturb any of the functions of the device. the device can still access mass storage at the same time the pc is synchronizing with the main processor. the slim architecture enables new usage models in which a pc can access a mass storage device independent of the main processor, or enumerate access to both the mass storage and the main processor at the same time. in a handset, this typically enables using the phone as a thumb drive, downloading media files to the phone while still having full functionality available on the phone, or using the same phone as a modem to connect the pc to the web. 8051 microprocessor the 8051 microprocessor embedded in astoria does basic trans- action management for all the transactions between p-port, s-port, and u-port. the 8051 does not reside in the data path; it manages the path. the data path is optimized for performance. the 8051 executes firmware that supports nand, sd, sdio, mmc+, and ce-ata devices at the s-port. for the nand device, the 8051 firmware follows the smart media algorithm to support: ? physical to logical management ? four random bits ecc detection and correction support ? wear leveling ? nand flash bad blocks handling configuration and status registers the west bridge astoria device includes configuration and status registers that are accessi ble as memory mapped registers through the processor interface. the configuration registers allow the system to specify ce rtain behavior of astoria. for example, it is able to mask certain status registers from raising an interrupt. the status register s convey various status, such as the addresses of buffers for read operations. processor interface (p-port) communication with the external processor is realized through a dedicated processor interface. th is interface is configured to support different interface standards. this interface supports multiplexing and nonmultiplexing address or data bus in both synchronous and asynchronous pseudo cram-mapped, and nonmultiplexing address or data asynchronous sram-mapped memory accesses. the interface also can be configured to a pseudo nand interface to su pport the processor?s nand interface. in addition, this inte rface can be configured to support spi slave. asynchronous accesses can reach a bandwidth of up to 66.7 mbps. synchronous a ccesses can be performed at 33 mhz across 16 bits for up to 66.7 mbps bandwidth. the memory address is decoded to access any of the multiple endpoint buffers inside astoria. these endpoints serve as buffers for data between each pair of ports, for example, between the processor port and the usb port. the processor writes and reads into these buffers via the memory interface. access to these buffers is controlled by either using a dma protocol or using an interrupt to the main processor. these two modes are configurable by the external processor. as a dma slave, astoria gener ates a dma request signal to signify to the main processor that a specific buffer is ready to be read from or written to. the external processor monitors this signal and polls astoria for the specific buffers ready for read or write. it then performs the appr opriate read or write operations on the buffer through the processor interface. this way, the external processor only deals wi th the buffers to access a multitude of storage devices connected to astoria. in the interrupt mode, astoria communicates important buffer status changes to the external processor using an interrupt signal. the external processor then polls astoria for the specific buffers ready for read or write, and it performs the appropriate read or write operations through the processor interface. usb interface (u-port) in accordance with the usb 2.0 specification, astoria can operate in full speed usb mode in addition to high speed usb. the usb interface consists of the usb transceiver. the usb interface is accessible by both the p-port and the s-port. the astoria usb interface supports programmable control/bulk/interrupt/is ochronous endpoints. astoria also has an integrated usb switch shown in figure 1 that allows interfacing to an external full speed usb phy. figure 1. u-port with switch and control block mass storage support (s-port) the s-port is configurable in six different interface modes, either simultaneously supporting an sd/sdio/mmc+/ce-ata port and a 8-bit slc or mlc nand flash ports, supporting two sd/sdio/mmc+/ce-ata ports, su pporting up to eight chip enable (ce#) for 8-bit or 16-bit slc or mlc nand flash port, supporting sd/sdio/mmc+/ce-ata port and gpio, supporting nand flash port and gpio, and gpio. these configurations are controlled by the 8051 firmware. the 16-bit nand flash interface can only be used when there is no other mass storage device connected to the s-port. d+ d- usb 2.0 xcvr usb port (u port) usb switch and control block swd+ swd- usballo uvalid [+] feedback
cywb0224abs, cywb0224abm cywb0226abs, cywb0226abm preliminary confidential page 3 of 7 n-xpress? nand controller (s-port) astoria, as part of its mass st orage management functions, fully manages the slc and mlc nand flash devices. the embedded 8051 manages the actual reading and writing of the nand along with its required protocols. it performs standard nand management functions such as ecc and wear leveling. the astoria supports single bit ecc for the slc and 4-bit ecc for mlc nand flash. slc nand flash devices are supported by cywb0244abs. cywb0244abm supports both slc and mlc nand flash devices. s-port configuration modes the s port is configurable in six different interface modes. ? nand flash and sd/sdio/mmc/ce-ata interface mode ? nand flash interface mode ? dual sd/sdio/mmc/ce-ata interface mode ? sd/sdio/mmc/ce-ata and gpio interface mode ? nand flash and gpio interface mode ? gpio interface mode nand flash interface mode the nand flash interface mode configures the s-port to interface with nand flash devices only. in this interface mode, the s-port is configured to inte rface up to sixteen 8-bit slc or mlc nand flash nand port (s-port) astoria, as part of its mass st orage management functions, fully manages the slc and mlc nand flash devices. the embedded 8051 sets up reading and writing transaction of the nand along with its required protocols. it performs standard nand management functions such as ecc and wear leveling. the astoria supports single bit ecc for the slc and four bytes random ecc detection and correction for mlc nand flash. slc nand flash devices are supported by cywb0244abs. cywb0244abm supports both slc and mlc nand flash devices. sd/sdio/mmc+/ce-ata port (s-port) when astoria is configured with firmware to support sd, sdio, mmc+, and ce-ata, this interface supports: ? the multimedia card system sp ecification, mmca technical committee, version 4.1. ? sd memory card specification - part 1, physical layer speci- fication, sd group, version 1.10, october 15, 2004. ? sd memory card specification - part 1, physical layer speci- fication, sd group, version 2.0, may 9, 2006. ? sd specifications - part e1 sd io specification, version 1.10, august 18, 2004. ? ce-ata specification - ce-ata digital protocol, ce-ata committee, version 1.1, september, 2005. west bridge astoria provides support for 1-bit and 4-bit sd and sdio cards, 1-bit, 4-bit and 8-bit mmc, mmc+ cards, and ce-ata drive. for the sd, sdio, mmc/mmc plus, and ce-ata, this block supports one card for one physical bus interface. astoria supports sd commands including the multisector program command that are handled by the api. [+] feedback
cywb0224abs, cywb0224abm cywb0226abs, cywb0226abm preliminary confidential page 4 of 7 pin assignments table 1. astoria pin assignments pin name pin de- scription power domain p-port pcram non multiplexing io pcram multiplexing (adm) io sram io pnand io spi io clk (pull low in asyn mode) i clk (pull -low in async mode) i ext pull low i ext pull low i sck i clock pvddq vgnd ce# i ce# i ce# i ce# i ss# i chip enable/pna nd chip select/spi slave select a0 i ext pull-up i a0 i cle i ext pull-up i addr. bus 0/pnand command latch a1 i ext pull-up i a1 i rb# o ext pull-up i addr. bus 1/pnand ready_buy a[3:2] i a[2] = 1 a[3] = don?t care i a[3:2] i a[3:2] = 00 i a[3:2] = 10 i addr. bus [3:2] a4 i ext pull-up i a4 i wp# i ext pull-up i addr. bus 4/pnand write protect a5 i scl io a5 i scl io scl io addr. bus 5/i2c clock a6 i sda io a6 i sda io sda io addr. bus 6/i2c data a7 i ext pull-up i a7 i a7 => 1:sbd a7 => 0: lbd i ext pull-up i addr. bus 7 dq[0] io ad[0] io dq[0] io io[0] io sdi i spi input/data bus 0 dq[1] io ad[1] io dq[1] io io[1] io sdo o spi output/data bus 1 dq[15:2] io ad[15:2] io dq[15:2] io io[15:2] io ext pull-up i data bus adv# i adv# i i ale i ext pull-up i address valid oe# i oe# i oe# i re# i ext pull-up i output enable we# i we# i we# i we# i ext pull-up i write enable drq & int int# o int# o int# o int# o sint# o interrupt request gvddq vgnd drq# o drq# o drq# o drq# o n/c o dma request dack# i dack# i dack# i dack# i ext pull-up i dma acknowl- edgement u-port d+ io/z usb d+ uvddq uvssq d- io/z usb d- swd+ io/z usb switch dp swd- io/z usb switch dm [+] feedback
cywb0224abs, cywb0224abm cywb0226abs, cywb0226abm preliminary confidential page 5 of 7 s-port sdio & nand configuration io nand only configuration io double sdio configuration io nand & gpio configuration io sdio & gpio configuration io gpio only configuration io sd_d[7:0] io nand_io[15:8] or pd[7:0] (gpio) io sd_d[7:0] io nand_io[15:8] or pd[7:0] (gpio) io sd_d[7:0] io pd[7:0] (gpio) io sd data bus/nand upper io bus ssvd- dq vgnd sd_clk o nand_ce8# or nand_r/b4# o i sd_clk o pc-7 (gpio) or nand_ce8# or nand_r/b4# io o i sd_clk pc-7 (gpio) io sd clock, nand ce8# or nand r/b4# sd_cmd io nand_ce7# or nand_r/b3# o i sd_cmd io pc-3 (gpio) or nand_ce7# or nand_r/b3# io o i sd_cmd io pc-3 (gpio) io sd command, nand ce7# or nand r/b4# sd_pow o nand_ce6# o sd_pow pc-6 (gpio) or nand_ce6# io o sd_pow pc-6 (gpio) io sd power control/na nd ce6# sd_wp i nand_ce5# o sd_wp i pc-5 (gpio) or nand_ce5# io sd_wp i n/c i gpio (sd write protection microswitch ) or nand ce5# nand_io[7:0] io nand_io[7:0] io sd2_d[7:0] io nand_io[7:0] o pb[7:0] (gpio) io pb[7:0] (gpio) io nand lower io bus snvd- dq vgnd nand_cle o nand_cle o sd2_clk o nand_cle o pa-6 (gpio) io pa-6 (gpio) io cmd latch enable nand_ale o nand_ale o sd2_cmd io nand_ale o p a-7 (gpio) io pa-7 (gpio) io address latch enable nand_ce# o nand_ce# o sd2_pow o nand_ce# o pc-0 (gpio) io pc-0 (gpio) io chip enable nand_re# o nand_re# o n/c o nand_re# o n/c o n/c o read enable nand_we# o nand_we# o n/c o nand_we# o n/c o n/c o write enable nand_wp# o nand_wp# o pa-5 (gpio) io nand_w p# i pa-5 (gpio) io pa-5 (gpio) io write protect nand_r/b# i nand_r/b# i n/c i nand_r/b# i n/c i n/c i ready/busy nand_ce2# o nand_ce2# o sd2_wp o nand_ce2# o pc-2 (gpio) io pc-2 (gpio) io chip enable 2 other resetout / nand_r/b2# o i nand_r/b2# i resetout o resetout or nand_r/b2# 0 i resetout o resetout o reset out or nand busy/ready gvddq vgnd pc-4 (gpio[0]) / sd_cd / nand_ce4# io i o nand_ce4# o pc-4 (gpio[0]) / sd_cd io i pc-4 (gpio[0]) or nand_ce4# io o pc-4 (gpio[0]) or sd_cd io i pc-4 (gpio[0]) io general input/output 0 or sd/mmc card detection or nand ce4# pc-5 (gpio[1]) / nand_ce3# io o nand_ce3# o pc-5 (gpio[1]) / sd2_cd io i pc-5 (gpio[1]) or nand_ce3# io o pc-5 (gpio[1]) io pc-5 (gpio[1]) io general input/output 1, nand ce3#, or sd2_cd reset# i reset wakeup i wake up signal conf xtalslc[1:0] i clock select 0 and 1 gvddq vgnd test[2:0] i test config- uration clock xtalin i crystal/cloc k in xvddq vgnd xtalout o crystal out table 1. astoria pin assignments (continued) [+] feedback
cywb0224abs, cywb0224abm cywb0226abs, cywb0226abm preliminary confidential page 6 of 7 power pvddq power processor i/f vdd snvddq power nand vdd uvddq power usb vdd ssvddq power sdio vdd gvddq power misc io vdd avddq power analog vdd xvddq power crystal vdd vdd power core vdd vdd33 power independen t 3.3v uvssq power usb gnd avssq power analog gnd vgnd power core gnd ordering information ordering code package type nand flash support available clock input frequencies (mhz) cywb0224abs-bvxi 100 vfbga ? pb-free support slc nand fl ash only 19.2, 24, 26, 48 CYWB0224ABM-BVXI 100 vfbga ? pb-free support slc and mlc nand flash 19.2, 24, 26, 48 cywb0226abs-bvxi 100 vfbga ? pb-fre e support slc nand flash and usb switch 19.2, 24, 26, 48 cywb0226abm-bvxi 100 vfbga ? pb-free support slc and mlc nand flash and usb switch 19.2, 24, 26, 48 table 1. astoria pin assignments (continued) [+] feedback
west bridge, astoria, antioch, and slim are trademarks of cypress semiconductor. all product and company names mentioned in thi s document are the trademarks of their respective holders. . preliminary confidential cywb0224abs, cywb0224abm cywb0226abs, cywb0226abm ? cypress semiconductor corporation, 2007-2008. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. package diagram figure 2. 100 vfbga (6 x 6 x 1.0 mm) bz100a a 1 a1 corner 0.50 0.50 ?0.300.05(100x) ?0.15 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.45 ref. 0.10 c 0.08 c a1 corner top view bottom view 2 3 4 4.50 4.50 b c d e f g h 65 46 5 23 1 6.000.10 6.000.10 a 6.000.10 6.000.10 b 2.25 2.25 0.21 ref. j reference jedec mo-195c pkg. weight: tbd (new pkg.) 7 8 9 10 78910 k g k j h d f e c b a 51-85209-*b [+] feedback
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